Why FIQ interrupt is enabled if TX_ENABLE_FIQ_SUPPORT is not defined in __tx_thread_preempt_restore function?

Question

Why FIQ interrupt is enabled if TX_ENABLE_FIQ_SUPPORT is not defined in __tx_thread_preempt_restore function?

Aniruddha Patel 36

I am looking at the port files for Azure RTOS for Cortex R5-F processor. I was looking at the tx_thread_context_restore.S file and I have following question.

In the function __tx_thread_preempt_restore, processor mode is temporarily changed from IRQ mode to SVC mode to save the registers on the stack of a thread which is being switched out. While changing the mode to SVC mode it seems that FIQ interrupts are enabled if macro TX_ENABLE_FIQ_SUPPORT is not defined, which seems wrong to me. In this case shouldn't it just change the processor mode and not modify FIQ bit of CPSR registers?

Following is the snippet of a function __tx_thread_preempt_restore for your reference.

__tx_thread_preempt_restore:
@
    LDMIA   sp!, {r3, r10, r12, lr}         @ Recover temporarily saved registers
    MOV     r1, lr                          @ Save lr (point of interrupt)
    MOV     r2, #SVC_MODE                   @ Build SVC mode CPSR
    MSR     CPSR_c, r2                      @ Enter SVC mode
    STR     r1, [sp, #-4]!                  @ Save point of interrupt
    STMDB   sp!, {r4-r12, lr}               @ Save upper half of registers
    MOV     r4, r3                          @ Save SPSR in r4
    MOV     r2, #IRQ_MODE                   @ Build IRQ mode CPSR
    MSR     CPSR_c, r2                      @ Enter IRQ mode
    LDMIA   sp!, {r0-r3}                    @ Recover r0-r3
    MOV     r5, #SVC_MODE                   @ Build SVC mode CPSR
    MSR     CPSR_c, r5                      @ Enter SVC mode
    STMDB   sp!, {r0-r3}                    @ Save r0-r3 on thread's stack
    ...
    ...

SVC_MODE and IRQ_MODE are defined as follows in the same file.

#ifdef TX_ENABLE_FIQ_SUPPORT
SVC_MODE        =     0xD3               @ Disable IRQ/FIQ, SVC mode
IRQ_MODE        =     0xD2               @ Disable IRQ/FIQ, IRQ mode
#else
SVC_MODE        =     0xD3               @ Disable IRQ, SVC mode
IRQ_MODE        =     0xD2               @ Disable IRQ, IRQ mode
#endif

It would be great if someone can clarify on this.

Thanks.

Aniruddha Patel 36 Reputation points

2020-09-04T20:51:23.243+00:00

The snippet of code I shared is for arm compiler 6 (ac6)
AshokPeddakotla-MSFT 35,971 Reputation points Moderator

2020-09-07T02:28:59.643+00:00

@Aniruddha Patel Welcome to Q&A forum!
Sorry for the inconvenience caused. We are looking into this issue and update you as earliest.
QuantumCache 20,366 Reputation points Moderator

2020-09-08T22:55:41.48+00:00

Hello @Aniruddha Patel , Sorry for the long delay, we are working with our team to clarify on this. Please stay tuned. Meanwhile please feel free to add your further questions on this thread.
Aniruddha Patel 36 Reputation points

2020-09-09T01:44:42.57+00:00

Thanks for the update @AshokPeddakotla-MSFT @QuantumCache . I appreciate it.

Accepted answer

1 additional answer

Your answer

Aniruddha Patel 36 Reputation points

2020-09-04T20:51:23.243+00:00

The snippet of code I shared is for arm compiler 6 (ac6)
AshokPeddakotla-MSFT 35,971 Reputation points Moderator

2020-09-07T02:28:59.643+00:00

@Aniruddha Patel Welcome to Q&A forum!
Sorry for the inconvenience caused. We are looking into this issue and update you as earliest.
QuantumCache 20,366 Reputation points Moderator

2020-09-08T22:55:41.48+00:00

Hello @Aniruddha Patel , Sorry for the long delay, we are working with our team to clarify on this. Please stay tuned. Meanwhile please feel free to add your further questions on this thread.
Aniruddha Patel 36 Reputation points

2020-09-09T01:44:42.57+00:00

Thanks for the update @AshokPeddakotla-MSFT @QuantumCache . I appreciate it.

Answer 1

Scott Azure RTOS 4,051

FIQ will remain enabled because no ThreadX APIs will be called in an FIQ (because TX_ENABLE_FIQ_SUPPORT is NOT defined). Remember: FIQs are still allowed to happen - ThreadX does not care what the user does in the FIQ (as long as the user does not call any ThreadX API).

Though I agree with you - the F bit should not be touched. I'll get our team to fix this.

Aniruddha Patel 36 Reputation points

2020-09-11T04:57:14.94+00:00

Thanks a lot @ScottLarson-6169 for the updates. I appreciate it.
AshokPeddakotla-MSFT 35,971 Reputation points Moderator

2020-09-16T13:33:59.757+00:00

@Aniruddha Patel Do you have any further queries?
Please accept helpful responses as 'Answer', which will be helpful to others as well.
Aniruddha Patel 36 Reputation points

2020-09-16T18:48:00.29+00:00

I couldn't accept comment as answer. If there is a way, please let me know and then I would accept the answer
QuantumCache 20,366 Reputation points Moderator

2020-09-16T18:50:53.383+00:00

Hello @Aniruddha Patel , please refer now for the responses, and please accept the helpful response as Answer.

Answer 2

Scott Azure RTOS 4,051

Hello,

For ARM Compiler 6, I see the following in this file (https://github.com/azure-rtos/threadx/blob/master/ports/cortex_r5/ac6/src/tx_thread_context_restore.S):

#ifdef TX_ENABLE_FIQ_SUPPORT
SVC_MODE        =     0xD3               @ Disable IRQ/FIQ, SVC mode
IRQ_MODE        =     0xD2               @ Disable IRQ/FIQ, IRQ mode
#else
SVC_MODE        =     0x93               @ Disable IRQ, SVC mode
IRQ_MODE        =     0x92               @ Disable IRQ, IRQ mode
#endif

So FIQ should be disabled.
What version are you looking at? What I linked to above is 6.0.1.

Thanks,
Scott

Aniruddha Patel 36 Reputation points

2020-09-09T18:07:42.26+00:00

Hi @ScottLarson-6169

For the case when TX_ENABLE_FIQ_SUPPORT is not defined SVC_MODE = 0x93 and IRQ_MODE = 0x92. These values set the bit corresponding to FIQ (bit 6) to 0. Since FIQ bit in CPSR for cortex r5F processor is active low, it enables the FIQ interrupts.

In the question by mistake I copied the same values for SVC_MODE and IRQ_MODE for both the cases when TX_ENABLE_FIQ_SUPPORT is defined and not defined. I apologize for that.
Aniruddha Patel 36 Reputation points

2020-09-09T18:22:46.207+00:00

For the case where TX_ENABLE_FIQ_SUPPORT is not defined, I think that FIQ bit should be left unchanged meaning if it is enabled before execution of that instruction it should stay enabled and if it is disabled before executing that instruction it should stay disabled.
Aniruddha Patel 36 Reputation points

2020-09-11T00:00:35.83+00:00

Hello @AshokPeddakotla-MSFT @QuantumCache

Any updates on this?
QuantumCache 20,366 Reputation points Moderator

2020-09-11T00:03:12.753+00:00

Hello @Aniruddha Patel , we are checking on this, please stay tuned.

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Why FIQ interrupt is enabled if TX_ENABLE_FIQ_SUPPORT is not defined in __tx_thread_preempt_restore function?

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