Is this what info you would need?
www.passmark.com Memory settings Transfer rate 6400 MT/s Memory timings 32-40-40-84 Channel mode 2Memory capacity / benchmarks L1 cache 64 KB (309.8 GB/s) L2 cache 1024 KB (138.1 GB/s) L3 cache 65536 KB (77.3 GB/s) Physical RAM 63.2 GB (40343 MB/s) Latency 46.770 nsMemory SPD information
| Item | Slot #1 | Slot #2 | Slot #3 | Slot #4 |
|---|---|---|---|---|
| Ram Type | DDR5 | DDR5 | Not Populated | Not Populated |
| Maximum Clock Speed (MHz) | 3200 (XMP) | 3200 (XMP) | ||
| Maximum Transfer Speed (MT/s) | DDR5-6400 | DDR5-6400 | ||
| Maximum Bandwidth (MB/s) | PC5-25600 | PC5-25600 | ||
| Memory Capacity (MB) | 32768 | 32768 | ||
| DIMM Temperature | N/A | N/A | ||
| Jedec Manufacture Name | Corsair | Corsair | ||
| Search Amazon.com | Search! | Search! | ||
| SPD Revision | 1.0 | 1.0 | ||
| Registered | No | No | ||
| ECC | No | No | ||
| On-Die ECC | Yes | Yes | ||
| DIMM Slot # | 1 | 2 | ||
| Manufactured | Week 48 of Year 2023 | Week 48 of Year 2023 | ||
| Module Part # | CMH64GX5M2B6400C32 | CMH64GX5M2B6400C32 | ||
| Module Revision | 0x0 | 0x0 | ||
| Module Serial # | 00000000 (029e00234800000000) | 00000000 (029e00234800000000) | ||
| Module Manufacturing Location | 0 | 0 | ||
| # of Row Addressing Bits | 16 | 16 | ||
| # of Column Addressing Bits | 10 | 10 | ||
| # of Banks | 32 | 32 | ||
| # of Ranks | 2 | 2 | ||
| Device Width in Bits | 8 | 8 | ||
| Bus Width in Bits | 32 | 32 | ||
| Module Voltage | 1.1V | 1.1V | ||
| CAS Latencies Supported | 22 28 30 32 36 40 42 | 22 28 30 32 36 40 42 | ||
| Timings @ Max Frequency (JEDEC) | 40-40-40-77 | 40-40-40-77 | ||
| Maximum frequency (MHz) | 2400 | 2400 | ||
| Maximum Transfer Speed (MT/s) | DDR5-4800 | DDR5-4800 | ||
| Maximum Bandwidth (MB/s) | PC5-19200 | PC5-19200 | ||
| Minimum Clock Cycle Time, tCK (ns) | 0.416 | 0.416 | ||
| Minimum CAS Latency Time, tAA (ns) | 16.666 | 16.666 | ||
| Minimum RAS to CAS Delay, tRCD (ns) | 16.666 | 16.666 | ||
| Minimum Row Precharge Time, tRP (ns) | 16.666 | 16.666 | ||
| Minimum Active to Precharge Time, tRAS (ns) | 32.000 | 32.000 | ||
| Minimum Row Active to Row Active Delay, tRRD (ns) | 0.000 | 0.000 | ||
| Minimum Auto-Refresh to Active/Auto-Refresh Time, tRC (ns) | 48.666 | 48.666 | ||
| Minimum Auto-Refresh to Active/Auto-Refresh Command Period, tRFC (ns) | 295.000 | 295.000 | ||
| DDR5 Specific SPD Attributes | ||||
| Maximum Clock Cycle Time, tCKmax (ns) | 1.010 | 1.010 | ||
| Write Recovery time (ns) | 30.000 | 30.000 | ||
| Minimum Auto-Refresh to Active/Auto Refresh Command Period, tRFC2 (ns) | 160.000 | 160.000 | ||
| Minimum Auto-Refresh to Active/Auto Refresh Command Period, tRFC4 (ns) | 130.000 | 130.000 | ||
| Minimum Refresh Recovery Delay Time, tRFC1 (ns) | 0.000 | 0.000 | ||
| Minimum Refresh Recovery Delay Time, tRFC2 (ns) | 0.000 | 0.000 | ||
| Minimum Refresh Recovery Delay Time, tRFCsb (ns) | 0.000 | 0.000 | ||
| Module Type | UDIMM | UDIMM | ||
| Module information SPD revision | 1.0 | 1.0 | ||
| SPD present | Yes | Yes | ||
| SPD device type | SPD5118 | SPD5118 | ||
| SPD Manufacturer | Montage Technology Group (Bank: 7, ID: 0x32) | Montage Technology Group (Bank: 7, ID: 0x32) | ||
| PMIC 0 present | Yes | Yes | ||
| PMIC 0 device type | PMIC5100 | PMIC5100 | ||
| PMIC 0 Manufacturer | Richtek Power (Bank: 11, ID: 0x8C) | Richtek Power (Bank: 11, ID: 0x8C) | ||
| PMIC 1 present | No | No | ||
| PMIC 1 device type | ||||
| PMIC 1 Manufacturer | ||||
| PMIC 2 present | No | No | ||
| PMIC 2 device type | ||||
| PMIC 2 Manufacturer | ||||
| Thermal Sensor 0 present | No | No | ||
| Thermal Sensor 1 present | No | No | ||
| Thermal Sensor device type | ||||
| Thermal Sensor Manufacturer | ||||
| Module Height (mm) | 45 | 45 | ||
| Module Thickness Front (mm) | 4 | 4 | ||
| Module Thickness Back (mm) | 4 | 4 | ||
| Module Reference Card | Raw Card B Rev. 0 | Raw Card B Rev. 0 | ||
| # DRAM Rows | 1 | 1 | ||
| Heat spreader installed | Yes | Yes | ||
| Operating Temperature Range | XT (0 to + 95 �C) | XT (0 to + 95 �C) | ||
| Rank Mix | Symmetrical | Symmetrical | ||
| Number of Package Ranks per Channel | 2 | 2 | ||
| Number of Channels per DIMM | 2 | 2 | ||
| Primary bus width per Channel | 32 bits | 32 bits | ||
| Bus width extension per Channel | 0 bits | 0 bits | ||
| DRAM Manufacture ID | 173 | 173 | ||
| DRAM Manufacture Bank | 1 | 1 | ||
| DRAM Manufacture Name | SK Hynix | SK Hynix | ||
| DRAM Stepping | 4.1 | 4.1 | ||
| SDRAM Package Type | Monolithic SDRAM | Monolithic SDRAM | ||
| SDRAM Density Per Die | 16Gb | 16Gb | ||
| SDRAM Bank Groups | 8 | 8 | ||
| SDRAM Banks Per Bank Group | 4 | 4 | ||
| Second SDRAM Package Type | ||||
| Second SDRAM Density Per Die | ||||
| Second SDRAM Column Address Bits | ||||
| Second SDRAM Row Address Bits | ||||
| Second SDRAM Device Width | ||||
| Second SDRAM Bank Groups | ||||
| Second SDRAM Banks Per Bank Group | ||||
| First SDRAM RFM RAAMMT | 0X (FGR: 0X) | 0X (FGR: 0X) | ||
| First SDRAM RFM RAAIMT | 0 (FGR: 0) | 0 (FGR: 0) | ||
| First SDRAM RFM Required | no | no | ||
| First SDRAM RFM RAA Counter Decrement per REF command | RAAIMT / 2 | RAAIMT / 2 | ||
| Second SDRAM RFM RAAMMT | ||||
| Second SDRAM RFM RAAIMT | ||||
| Second SDRAM RFM Required | ||||
| Second SDRAM RFM RAA Counter Decrement per REF command | ||||
| First SDRAM ARFM Level A RAAMMT | 0X (FGR: 0X) | 0X (FGR: 0X) | ||
| First SDRAM ARFM Level A RAAIMT | 0 (FGR: 0) | 0 (FGR: 0) | ||
| First SDRAM ARFM Level A supported | no | no | ||
| First SDRAM ARFM Level A RAA Counter Decrement per REF command | RAAIMT / 2 | RAAIMT / 2 | ||
| Second SDRAM ARFM Level A RAAMMT | ||||
| Second SDRAM ARFM Level A RAAIMT | ||||
| Second SDRAM ARFM Level A supported | ||||
| Second SDRAM ARFM Level A RAA Counter Decrement per REF command | ||||
| First SDRAM ARFM Level B RAAMMT | 0X (FGR: 0X) | 0X (FGR: 0X) | ||
| First SDRAM ARFM Level B RAAIMT | 0 (FGR: 0) | 0 (FGR: 0) | ||
| First SDRAM ARFM Level B supported | no | no | ||
| First SDRAM ARFM Level B RAA Counter Decrement per REF command | RAAIMT / 2 | RAAIMT / 2 | ||
| Second SDRAM ARFM Level B RAAMMT | ||||
| Second SDRAM ARFM Level B RAAIMT | ||||
| Second SDRAM ARFM Level B supported | ||||
| Second SDRAM ARFM Level B RAA Counter Decrement per REF command | ||||
| First SDRAM ARFM Level C RAAMMT | 0X (FGR: 0X) | 0X (FGR: 0X) | ||
| First SDRAM ARFM Level C RAAIMT | 0 (FGR: 0) | 0 (FGR: 0) | ||
| First SDRAM ARFM Level C supported | no | no | ||
| First SDRAM ARFM Level C RAA Counter Decrement per REF command | RAAIMT / 2 | RAAIMT / 2 | ||
| Second SDRAM ARFM Level C RAAMMT | ||||
| Second SDRAM ARFM Level C RAAIMT | ||||
| Second SDRAM ARFM Level C supported | ||||
| Second SDRAM ARFM Level C RAA Counter Decrement per REF command | ||||
| sPPR Granularity | bank group | bank group | ||
| sPPR Undo/Lock | supported | supported | ||
| Burst length 32 | not supported | not supported | ||
| MBIST/mPPR | not supported | not supported | ||
| mPPR/hPPR Abort | not supported | not supported | ||
| PASR | not supported | not supported | ||
| DCA Types Supported | Device does not support DCA | Device does not support DCA | ||
| x4 RMW/ECS Writeback Suppression | not supported | not supported | ||
| x4 RMW/ECS Writeback Suppression MR selector | MR9 | MR9 | ||
| Bounded Fault | not supported | not supported | ||
| SDRAM Nominal Voltage, VDDQ | 1.1V | 1.1V | ||
| SDRAM Nominal Voltage, VPP | 1.8V | 1.8V | ||
| Cyclical Redundancy Code (CRC) for Base Configuration | fb18 | fb18 | ||
| XMP Attributes | ||||
| XMP version | 3.0 | 3.0 | ||
| PMIC Vendor ID | 8A8C | 8A8C | ||
| Number of PMICs on DIMM | 1 | 1 | ||
| PMIC capabilities | ||||
| PMIC has capabilities for OC functions | No | No | ||
| Current PMIC OC is enabled | No | No | ||
| PMIC voltage default step size | 5mV | 5mV | ||
| OC global reset functions | No | No | ||
| Validation and Certification Capabilities | ||||
| DIMM is self-certified by DIMM vendor | No | No | ||
| PMIC Component is validated by Intel AVL level | No | No | ||
| XMP revision | 1.2 | 1.2 | ||
| XMP Profile 1 | ||||
| Profile name | Profile 1 | Profile 1 | ||
| XMP Certified | No | No | ||
| Recommended number of DIMMs per channel | 1 | 1 | ||
| Module VPP voltage | 1.80V | 1.80V | ||
| Module VDD voltage | 1.40V | 1.40V | ||
| Module VDDQ voltage | 1.40V | 1.40V | ||
| Memory Controller voltage | 1.20V | 1.20V | ||
| Clock speed (MHz) | 3200 | 3200 | ||
| Transfer Speed (MT/s) | DDR5-6400 | DDR5-6400 | ||
| Bandwidth (MB/s) | PC5-25600 | PC5-25600 | ||
| Minimum clock cycle time, tCK (ns) | 0.312 | 0.312 | ||
| Supported CAS latencies | 22 26 28 30 32 36 40 42 46 48 50 52 54 56 | 22 26 28 30 32 36 40 42 46 48 50 52 54 56 | ||
| Minimum CAS latency time, tAA (ns) | 9.984 | 9.984 | ||
| Minimum RAS to CAS delay time, tRCD (ns) | 12.480 | 12.480 | ||
| Minimum row precharge time, tRP (ns) | 12.480 | 12.480 | ||
| Minimum active to precharge time, tRAS (ns) | 26.208 | 26.208 | ||
| Supported timing at highest clock speed | 32-40-40-84 | 32-40-40-84 | ||
| Minimum Active to Auto-Refresh Delay, tRC (ns) | 38.688 | 38.688 | ||
| Minimum Write Recovery Time, tWR (ns) | 30.000 | 30.000 | ||
| Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC1 (ns) | 295.000 | 295.000 | ||
| Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC2 (ns) | 160.000 | 160.000 | ||
| Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFCsb (ns) | 130.000 | 130.000 | ||
| Minimum Read to Read Command Delay Time, Same Bank Group, tCCD_L (ns) | 5.000 (8 nCK) | 5.000 (8 nCK) | ||
| Minimum Write to Write Command Delay Time, Same Bank Group, tCCD_L_WR (ns) | 20.000 (32 nCK) | 20.000 (32 nCK) | ||
| Minimum Write to Write Command Delay Time, Second Write not RMW, Same Bank Group, tCCD_L_WR2 (ns) | 10.000 (16 nCK) | 10.000 (16 nCK) | ||
| Minimum Write to Read Command Delay Time, Same Bank Group, tCCD_L_WTR (ns) | 10.000 (16 nCK) | 10.000 (16 nCK) | ||
| Minimum Write to Read Command Delay Time, Different Bank Group, tCCD_S_WTR (ns) | 2.500 (4 nCK) | 2.500 (4 nCK) | ||
| Minimum Active to Active Command Delay Time, Same Bank Group, tRRD_L (ns) | 5.000 (8 nCK) | 5.000 (8 nCK) | ||
| Minimum Read to Precharge Command Delay Time, tRTP (ns) | 7.500 (12 nCK) | 7.500 (12 nCK) | ||
| Minimum Four Activate Window, tFAW (ns) | 10.000 | 10.000 | ||
| Advanced Memory Overclocking Features | ||||
| Real-Time Memory Frequency Overclocking | Supported | Supported | ||
| Intel Dynamic Memory Boost | Supported | Supported | ||
| System CMD Rate Mode | 2N | 2N | ||
| Vendor Personality Byte | 0x00 | 0x00 |