Hello @Simon Luk - The first write sets the initial erase count to 1, but also maintains the erased bit – bit 31. The next write clears the erased bit and maintains the new erase count of 1. The LevelX code generally prefers to manipulate each field in discrete steps.
Question about LevelX source code in file lx_nand_flash_open.c.
Simon Luk
56
Reputation points
LevelX version 6.1.3
could not understand file lx_nand_flash_open.c, between line 282 to 297
why do the _lx_nand_flash_driver_write() twice?
/* Setup the initial erase count to 1. */
page_word_ptr[0] = (((ULONG) 1) | LX_BLOCK_ERASED);
/* Write the initial erase count for the block. */
status = _lx_nand_flash_driver_write(nand_flash, block, 0, page_word_ptr, LX_NAND_ERASE_COUNT_WRITE_SIZE);
/* Check for status after the block erase. */
if (status == LX_SUCCESS)
{
/* Setup the initial erase count to 1. */
page_word_ptr[0] = ((ULONG) 1);
/* Write the initial erase count for the block. */
status = _lx_nand_flash_driver_write(nand_flash, block, 0, page_word_ptr, LX_NAND_ERASE_COUNT_WRITE_SIZE);
}
Azure RTOS
Azure RTOS
An Azure embedded development suite including a small but powerful operating system for resource-constrained devices.
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本权 张 1 Reputation point
2021-07-02T06:40:33.42+00:00 this operation will cause problems in NAND ECC calculation. ECC code will be stored in the first write, and problems will occur in the second write,then LevelX only use for
none ECC case?