X64 Article Questions & Clarifications

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Finally, a response to some comments and questions about my x64 article.

Registry Fun

Noah Harrison thinks I got it backwards when I said: "As you'd expect, the OS provides an escape hatch for 32-bit applications to read the actual 64-bit registry value by specifying new flag values when calling RegOpenKey and friends."

To be honest, I'm not 100% sure. Try as I might, I'm unable to find the original source where I came up with the bit about a flag to RegOpenKey. It may exist, I'm just not finding it at the moment. Meanwhile, I realized that I didn't mention the RegDisableReflectKey API, which allows doing what I originally claimed.

Handle Sizes

Despite many reviews by myself and others, this snippet slipped by: "That is, a 64-bit pointer is 8 bytes, while int, long, DWORD, and HANDLE are still 4 bytes."

Handles are in fact defined as pointer values:

typedef

void *HANDLE;

Thus, in a Win64 world, a handle is 8 bytes. No real excuse for my slipup on this one. Just an over-generalization on my part.

Debug Registers

Nilesh Padribi asked about Debug Register support on the X64 CPU. The short version of the story is that the x86 debug registers are widened to 64-bits, and that's pretty much it. The longer version comes from the AMD documentation:

Like the control registers, debug registers DR0

–DR7 are expanded to 64 bits. In 64-bit mode, the MOV DRn instructions read or write all 64 register bits. Operand-size prefixes are ignored.

In all 16-bit or 32-bit modes (legacy or compatibility modes), writes to a debug register fill the upper 32 bits with zeros and reads from a debug register return only the lower 32 bits.

In 64-bit mode, the upper 32 bits of DR6 and DR7 are reserved and must be written with zeros. Writing a 1 to any of the upper 32 bits results in a general-protection exception, #GP(0). All 64 bits of DR0

–DR3 are writable by software. However, the MOV DRn instructions do not check that addresses written to DR0–DR3 are within the virtual-address limits of the implementation.

Also, a related note in another section of the AMD doc states that encodings are available for another eight registers (DR8-DR15), but that the current CPUs don't implement those registers.