SHx Microprocessor
Other versions of this page are also available for the following:
.gif "A hyphen indicates that the information in this topic is not relevant for this platform, or that the platform does not support the API that is listed.")
.gif "A checkmark indicates that the information in this topic is relevant for this platform, and that any API listed is also supported on this platform.")
8/27/2008
All SHx interrupt service routines (ISRs) can be written in C. Any volatile registers can be used in accordance with the C calling convention without using save/restore. Specifically, an SHx ISR can use registers r0 through r7.
Use the following design principals when creating an OAL for an SHx microprocessor:
The ISR must return by means of rts, and cannot access any addresses through the translation look-aside buffer (TLB).
Implement the nonmaskable-interrupt ISR, OEMNMI.
OEMInit must register OEMNMI.
You can define the variable OEMExtraCCR to configure the cache control register. The default value is 0.
Note
To place an SH4 device in write-through mode, reset the cache control register (CCR) to write-through mode in OEMInit.
Nested interrupts.
The SHx kernel utilizes a structure that provides the kernel with information about which nested interrupts are masked while the current interrupt is being handled. To gain access to this structure, the IntrPrio global variable must be declared in the OAL.
See Also
Tasks
How to Develop an OEM Adaptation Layer