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pOEMIsProcessorFeaturePresent (Windows Embedded CE 6.0)

1/5/2010

This function points to the IsProcessorFeaturePresent function, if defined.

OEMs should implement this function if the processor supports extended features.

Syntax

extern BOOL (*pOEMIsProcessorFeaturePresent)(
  DWORD dwProcessorFeature
);

Parameters

  • dwProcessorFeature
    [in] Specifies the flag for the feature that you want to verify support for.

    The following table shows the flags for ARM processor features.

    Flag Description

    PF_ARM_V4

    ARM architecture v4

    PF_ARM_V5

    ARM architecture v5

    PF_ARM_V6

    ARM architecture v6

    PF_ARM_V7

    ARM architecture v7

    PF_ARM_THUMB

    Thumb instruction set

    PF_ARM_JAZELLE

    ARM Jazelle technology

    PF_ARM_DSP

    'E' DSP instructions

    This flag is deprecated, but no additional flag is required because this is covered by ARMv5 and later.

    PF_ARM_MOVE_CP

    ARM MOVE coprocessor

    PF_ARM_VFP10

    VFP10 floating-point unit (FPU)

    This flag is deprecated. For the correct flags to use, please see the other VFP flags.

    PF_ARM_MPU

    Support for memory protection unit (MPU) is available

    PF_ARM_WRITE_BUFFER

    Writeback buffer

    PF_ARM_MBX

    ARM MBX technology

    PF_ARM_L2CACHE

    Level 2 cache controller

    This flag is deprecated. For the correct flags to use, see the other L2 cache flags.

    PF_ARM_PHYSICALLY_TAGGED_CACHE

    Cache is, or can be, physically tagged

    PF_ARM_VFP_SINGLE_PRECISION

    Single precision vectored floating-point unit

    PF_ARM_VFP_DOUBLE_PRECISION

    Double precision vectored floating-point unit

    PF_ARM_ITCM

    Tightly-coupled data memory

    PF_ARM_DTCM

    Tightly-coupled data memory

    PF_ARM_UNIFIED_CACHE

    Unified cache

    PF_ARM_WRITE_BACK_CACHE

    Writeback cache

    PF_ARM_CACHE_CAN_BE_LOCKED_DOWN

    Cache can be locked down

    PF_ARM_L2CACHE_MEMORY_MAPPED

    Level 2 cache controller implemented as a memory-mapped peripheral

    PF_ARM_L2CACHE_COPROC

    Level 2 cache controller implemented as a coprocessor

    PF_ARM_INTEL_XSCALE

    Intel XScale processor

    This can be used to determine if the processor supports operations where src==dest.

    PF_ARM_INTEL_PMU

    Performance Monitor Unit (PMU)

    PF_ARM_INTEL_WMMX

    WMMX support

    The following table shows the flags for MIPS processor features.

    Flag Description

    PF_MIPS_MIPSII

    MIPSII instruction set

    PF_MIPS_MIPSIII

    MIPSIII instruction set

    PF_MIPS_MIPSIV

    MIPSIV instruction set

    PF_MIPS_SMART_ASE

    MIPS smart card architecture specific extension

    PF_MIPS_MIPS16

    MIPS16 instruction set

    PF_MIPS_MIPS32

    MIPS32 instruction set

    PF_MIPS_MIPS64

    MIPS64 instruction set

    PF_MIPS_FPU

    FPU support

    PF_MIPS_CPU_4KEX

    R4K exception model

    PF_MIPS_CPU_4KTLB

    R4K translation look-aside buffer (TLB) handler

    PF_MIPS_CPU_32FPR

    32 double precision FP registers

    PF_MIPS_CPU_COUNTER

    Cycle count or compare

    PF_MIPS_CPU_WATCH

    Watchpoint registers

    PF_MIPS_CPU_DIVEC

    Dedicated interrupt vector

    PF_MIPS_CPU_VCE

    Virtual coherence conflict

    PF_MIPS_CPU_CACHE_CDEX

    Create_Dirty_Exclusive cache operation

    PF_MIPS_CPU_MCHECK

    Machine check exception

    PF_MIPS_CPU_EJTAG

    EJTAG exception

    PF_MIPS_PERF_COUNTER

    Performance counter

    PF_MIPS_ARCH_2

    Architecture release 2

    The following table shows the flags for SHx processor features.

    Flag Description

    PF_SHX_SH3

    SH3 instruction set

    PF_SHX_SH4

    SH4 instruction set

    PF_SHX_SH5

    SH5 instruction set

    PF_SHX_DSP

    Digital signal processor (DSP)

    PF_SHX_FPU

    Floating-point unit

    The following table shows the flags for x86 processor features.

    Flag Description

    PF_FLOATING_POINT_PRECISION_ERRATA

    Floating-point precision error

    PF_FLOATING_POINT_EMULATED

    Floating-point operations are emulated

    PF_COMPARE_EXCHANGE_DOUBLE

    Compare and exchange double operation

    PF_MMX_INSTRUCTIONS_AVAILABLE

    MMX instruction set

    PF_XMMI_INSTRUCTIONS_AVAILABLE

    SSE instruction set

    PF_3DNOW_INSTRUCTIONS_AVAILABLE

    3D-Now instruction set

    PF_RDTSC_INSTRUCTION_AVAILABLE

    RDTSC instruction

    Note

    All other PF_XXX flags to pOEMIsProcessorFeaturePresent return FALSE.

Return Value

Returns nonzero if the processor feature is supported; otherwise, the function returns FALSE.

Remarks

The PF_XXX flags in dwProcessorFeature are filtered based on the CPU type. Depending on the processor being compiled, only the PF_XXX flags corresponding to your CPU are present. If you verify support for an unsupported feature, the function returns FALSE.

Requirements

Header Developer Implemented
Library OEMMain.lib or OEMMain_StaticKITL.lib
Windows Embedded CE Windows CE 5.0 and later

See Also

Reference

Optional OAL Functions

Other Resources

IsProcessorFeaturePresent