DSP Unit Registers
The SH3-DSP 7729 has eight data registers and one control register. With the exception of registers A1 and A0, the data registers are 32-bit width. Registers A0 and A1 also include eight guard bits in fields A0G and A1G, giving them a total width of 40 bits.
The following list shows the three kinds of operation that access the DSP data registers:
DSP data processing
When a DSP fixed-point data operation uses A0 or A1 as the source register, it uses the guard bits 39–32. When it uses A0 or A1 as the destination register, guard bits 39–32 are valid. When a DSP fixed-point data operation uses a DSP register other than A0 or A1 as the source register, it sign-extends the source value to bits 39–32. When it uses one of these registers as the destination register, it discards bits 39–32 of the result.
X or Y data transfer operation, MOVX.W and MOVY.W.
This operation accesses the X and Y memories through the 16-bit X and Y data buses. The register to be loaded or stored by this operation always includes the upper 16 bits, bits 31–16. X0 or X1 can be the destination of an X memory load and Y0 or Y1 can be the destination of a Y memory load, but no other register can be the destination register in this operation. When data is read into the upper 16 bits of a register, the lower 16 bits of the register, bits 0-15, are automatically cleared. A0 and A1 can be stored in the X or Y memory by this operation, but no other registers can be stored.
Single-data transfer instruction, MOVS.W or MOVS.L.
These instructions access any memory location through the LDB. All DSP registers connect to the LDB and can be the source or destination register of the data transfer. These instructions have word and longword access modes. In word mode, registers to be loaded or stored by this instruction make up the upper 16 bits for DSP registers except A0G and A1G. When data is loaded into a register other than A0G and A1G in word mode, the lower half of the register is cleared. When A0 or A1 is used, the data is sign-extended to bits 39–32 and the lower half is cleared. When A0G or A1G is the destination register in word mode, data is loaded into an 8-bit register, but A0 and A1 are not cleared. In longword mode, when the destination register is A0 or A1, it is sign-extended to bits 39–32.
The DSP unit has one control register, the DSP status register (DSR). DSR holds the status of DSP data operation results such as zero, negative, and so on, and has a DC bit which is similar to the T bit in the CPU. The DC bit indicates one of the status flags. A DSP data processing instruction controls its execution based on the DC bit. This control affects only the operations in the DSP unit; it controls the update of DSP registers only. It cannot control operations in the CPU, such as address register updating and load/store operations. Control bits CS [2:0] specify the condition to be reflected in the DC bit.
Unconditional DSP type data operations, except PMULS, MOVX, MOVY and MOVS, update the condition flags and DC bit, but no CPU instructions, including MAC instructions, update the DC bit. In addition, conditional DSP type instructions do NOT update DSR.
The following table describes the DSP bits.
| Bits | Description |
|---|---|
| 31–8 Reserved bits |
0: Always read as 0; always use 0 as the write value |
| 7 Signed greater-than bit (GT) |
Indicates that the operation result is positive, except 0, or that operand 1 is greater than operand 2 |
| 6 Zero bit (Z) |
Indicates that the operation result is zero (0), or that operand 1 is equal to operand 2 |
| 5 Negative bit (N) |
Indicates that the operation result is negative, or that operand 1 is smaller than operand 2 |
| 4 Overflow bit (V) |
Indicates that the operation result has overflowed |
| 3–1 Condition Select bits (CS) |
Designates the mode for selecting the operation result status to be set in the DC bit. Do not set these bits to 110 or 111.
|
| 0 DSP Condition bit (DC) |
Sets the status of the operation result in the mode designated by the CS bits
|
SH3-DSP assigns DSR system register, and provides the following load/store instructions:
- STS DSR,Rn;
- STS.L DSR,@-Rn;
- **LDS.L @Rn+,DSR;**
- LDS Rn,DSR;
When an STS instruction reads DSR, the upper bits are all zero.
See Also
SH3-DSP Registers | SH3-DSP General Registers | SH3-DSP Status Registers | SH3-DSP Control Registers | RS, RE, and ME Control Registers | SH3-DSP System Registers
Last updated on Thursday, April 08, 2004
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