SHx Kernels
Before control is transferred to the kernel, the boot loader passes control to the StartUp routine to put the CPU into as initialized state. Platform Builder ships with two SHx based BSPs for which the StartUp function is specified in the source file directories in the following table.
| BSP | Source file |
|---|---|
| Hitachi US7729 HARP (Keywest) - SH3 | %_WINCEROOT%\Platform\Keywest\Kernel\Hal\SH |
| Hitachi US9950 HARP (Aspen) - SH4 | %_WINCEROOT%\Platform\Aspen\Kernel\Hal\SH |
OEMs developing for the SHx processor using the SHx kernel are expected to perform the following tasks:
- Set up bus state control registers
- Set up frequency control registers
- Disable cache
- Initialize SDRAM (SH3 only)
- Initialize watchdog timer
When the FRQ Control Register is modified it creates instability in the PLL. For this reason, when FRQCR is modified, the CPU shuts off. The watchdog timer can be programmed to cause a system wakeup with an interval of 0.
Until the bus controller has been initialized, some of debug devices, such as discrete LEDs and timing loops, may not be correct. BCR1 sets the types of memory that are being used. BCR2 is used to set the bus widths of all of the memory areas.
Initialize the SDRAM memory in Area 3 (SH3 specific). Load the SDRAM mode register by appending the initialization value with the lower address bits of the memory area reserved by the SH3. Because the lower two address bits are not connected to the SDRAM chips (A0 & A1), you must shift the value left by two bits.
See Also
CPU Initialization | OAL StartUp Function Implementation
Last updated on Wednesday, April 13, 2005
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