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SHx Microprocessor

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SH3 interrupt service routines (ISRs) are limited to using a subset of the available microprocessor registers. Specifically, an SH3 ISR can only use registers r0, r1, r2, r3, and r6. Use the following design principals when creating an OAL for an SHx microprocessor:

  • The ISR must return by means of rts, and cannot access any addresses through the translation look-aside buffer (TLB).

  • Implement the nonmaskable-interrupt ISR, OEMNMI.

  • OEMInit must register OEMNMI.

  • You can define the variable OEMExtraCCR to configure the cache control register. The default value is 0.

    Note   To place an SH4 device in write-through mode, reset the cache control register (CCR) to write-through mode in OEMInit.

  • The scheduler timer code is implemented in the Ktimer.c and Timer0.src files in the OAL. Sample versions of these files are located in %_WINCEROOT%\Platform\%BSP%\Kernel\Hal\Shx.

  • Nested interrupts.

    The SHx kernel utilizes a structure that provides the kernel with information about which nested interrupts are masked while the current interrupt is being handled. To gain access to this structure, the IntrPrio global variable must be declared in the OAL.

See Also

How to Develop an OEM Adaptation Layer | Microprocessor-specific Issues

Last updated on Wednesday, April 13, 2005

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