Microprocessor Changes (Windows CE 5.0)
When you reference microprocessors in Windows CE .NET 4.0 and later, keep the following changes in mind:
Microprocessor-specific defines, such as R4100, R4102, R4111, R4200, R4300, IDT32364, ARM720, and ARM920, should no longer be used outside of the kernel.
Although R4100 and IDT32364 are both MIPS II architectures, they are now built on slightly different translation look-aside buffers (TLBs).
The MIPS II Sysgen variable creates two variants of the kernel Nk.bin file.
SHx is now in the SH microprocessor family.
The DIRS_SHx environment variable is now DIRS_SH. Paths including SHx are now SH.
The _SH3_ macro previously applied to SH3 and SH4.
It has been replaced by _SHX_. The SHx macro is also available.
Microprocessor types now represent microprocessor architectures and many environment variables are different. The following table shows the previous microprocessor names and the new names for Wince.bat.
Previous microprocessor type and name New microprocessor name MIPS/R4100 MIPSII MIPS/IDT32364 MIPSII MIPS/R4300 MIPSII_FP MIPS/MIPSIV MIPSIV MIPS/MIPSIV_FP MIPSIV_FP ARM/ARM720, ARM/ARM920, and other ARM variants ARMV4I SHx/SH4 SH4 x86/i486 x86
The following table shows microprocessor-specific APIs that Windows CE requires. For a comprehensive list of all the required APIs, see the API reference topics.
| Microprocessor: language element |
Description |
|---|---|
| All microprocessors: GetIdleTime | In Windows CE 3.0 and later, supporting this function requires that you declare and calculate the following variables in the OAL:
|
| x86: IOCTL_HAL_REBOOT | In Windows CE .NET 4.1 and later, the x86 microprocessor implementation of IOCTL_HAL_REBOOT is unique because the OS includes conditionally compiled code that offers the following implementations:
The hardware reset signal is therefore asserted. This is the same as pressing the reset button, which causes the BIOS to run. |
| x86: OEMFlushCache | In Windows CE 3.0 and later, the OEMFlushCache function is needed for all x86 target devices. The kernel calls this function when the CacheSync function is called. |
| SHx: SH4CacheLines | In Windows CE .NET 4.1 and later, this variable describes the number of cache lines supported by the SH4 microprocessor. |
| SHx: Nested interrupts | In Windows CE .NET 4.0 and later, in the SHx architecture, the IntrPrio structure provides the kernel with information about which interrupts are masked when the current interrupt is handled.
To gain access to the structure, you must declare the |
| MIPS: Nested interrupts | In Windows CE .NET 4.0 and later, in the MIPS architecture, the kernel uses the IntrPriority and IntrMask structures to provide information about nested interrupts.
The structures provide the kernel with the information about which interrupts are masked when the current interrupt is handled. |
| ARM: OEMARMCacheMode | In Windows CE .NET 4.0 and later, this function allows you to change the cache bits settings in the page table entries for only the ARM processors. These bits determine cache mode and write buffer use.
The ARM kernels still default to their previous settings but in Windows CE you can change those settings and the ARM microprocessor supports the change. This function is required in every ARM OAL. |
| ARM: OEMInterruptHandlerFIQ | In Windows CE .NET 4.0 and later, Windows CE enables the routing of the fast Interrupt request (FIQ) OAL. To facilitate the routing, you must implement the OEMInterruptHandlerFIQ function.
This function must be part of the your OAL for any ARM build to succeed, even if it is just a stub. |
| ARM: OEMInterruptHandler | In Windows CE .NET 4.0 and later, Windows CE enables nesting support.
The kernel calls the OEMInterruptHandler function when a typical interrupt occurs. |
See Also
Migrating a Board Support Package | Debugging and Testing
Send Feedback on this topic to the authors