ld_structured (sm5 - asm)
Random-access read of 1-4 32bit components from a structured buffer.
|ld_structured dest[.mask], srcAddress[.select_component], srcByteOffset[.select_component], src0[.swizzle]|
||[in] The address of the results of the operation.
||[in] Specifies the index of the structure to read.
||[in] Specifies the byte offset in the structure to start reading from.
||The buffer to read from. This parameter must be a SRV (t#), UAV (u#). In the compute shader it can also be thread group shared memory (g#).
The data read from the structure is equivalent to the following pseudocode: where we have the offset, address, pointer to the buffer contents, stride of the source, and the data stored linearly.
BYTE *BufferContents; // from SRV or UAV UINT BufferStride; // from base resource UINT srcAddress, srcByteOffset; // from source registers BYTE *ReadLocation; // value to calculate ReadLocation = BufferContents + BufferStride * srcAddress + srcByteOffset; UINT32 Temp; // used to make code shorter // apply the source resource swizzle on source data Temp = read_and_swizzle(ReadLocation, srcSwizzle); // write the components to the output based on mask ApplyWriteMask(dstRegister, dstWriteMask, Temp);
This pseudocode shows how the operation functions, but the actual data does not have to be stored linearly. If the data is not stored linearly, the actual operation of the instruction needs to match the behavior of the above operation.
Out of bounds addressing on u#/t# of any given 32-bit component returns 0 for that component, except if srcByteOffset, plus swizzle is what causes out of bounds access to u#/t#, the returned value for all component(s) is undefined.
Out of bounds addressing on g# (the bounds of that particular g#, as opposed to all shared memory) for any given 32-bit component returns an undefined result.
srcByteOffset is a separate argument from srcAddress because it is commonly a literal. This parameter separation has not been done for atomics on structured memory.
cs_4_0 and cs_4_1 support this instruction for UAV, SRV, and TGSM.
This instruction applies to the following shader stages:
Because UAVs are available at all shader stages for Direct3D 11.1, this instruction applies to all shader stages for UAVs for the Direct3D 11.1 runtime, which is available starting with Windows 8.
Minimum Shader Model
This instruction is supported in the following shader models:
|Shader Model 5||yes|
|Shader Model 4.1||no|
|Shader Model 4||no|
|Shader Model 3 (DirectX HLSL)||no|
|Shader Model 2 (DirectX HLSL)||no|
|Shader Model 1 (DirectX HLSL)||no|
cs_4_0 and cs_4_1 support this instruction for UAV, SRV and TGSM.