vs_2_x
A programmable vertex shader is made up of a set of instructions that operate on vertex data. Registers transfer data in and out of the ALU. Additional control can be applied to modify the instruction, the results, or what data gets written out.
Vertex shader version vs_2_x extends the feature set supported by vs_2_0. Each additional feature is represented by a corresponding cap in the D3DCAPS9 structure within D3DVS20CAPS. To use any of the enhanced features represented by these caps, the vertex shader version must be specified as vs_2_x.
- Instructions - vs_2_x contains a list of the available instructions.
- Registers - vs_2_x lists the different types of registers used by the vertex shader ALU.
- Vertex Shader Register Modifiers are used to modify the way an instruction works.
- Vertex Shader Source Register Modifiers alter the source register data before the instruction runs.
- Source Register Swizzling gives additional control over which register components are read, copied, or written.
- Destination Register Masking determines what components of the destination register get written.
New Features
New features are as follows:
Dynamic Flow Control
If D3DVS20CAPS > 0, then the following dynamic flow control instructions are supported:
If D3DVS20CAPS is also set, the following additional flow control instructions are supported:
The range of values for dynamic flow control depth is 0 to 24 and is equal to the nesting depth of the dynamic flow control instructions (see Flow Control Nesting Limits for details). If this cap is zero, the device does not support dynamic flow control instructions.
Number of Temporary Registers
D3DVS20CAPS represents the number of Temporary Registers supported by the device. The range of values for this cap is 12 to 32.
Static Flow Control Nesting Depth
D3DVS20CAPS represents the nesting depth of two types of static flow control instructions: loop - vs/rep - vs and call - vs/callnz bool - vs/if bool - vs. loop - vs/rep - vs instructions can be nested up to D3DVS20CAPS deep. Independently, call - vs/callnz bool - vs instructions can be nested up to D3DVS20CAPS deep. If D3DVS20CAPS is also set, then callnz pred - vs is counted toward the nesting depth of call - vs/callnz bool - vs/if bool - vs (see Flow Control Nesting Limits for details).
Predication
If D3DVS20CAPS is set, the device supports setp_comp - vs and instruction predication. If D3DVS20CAPS is also greater than 0, then the following additional dynamic flow control instructions are supported:
Instruction Count
Each vertex shader can have up to 256 instructions stored. The number of instructions run can be much higher (because of the loop/rep support), and is capped by D3DCAPS9, which should be at least 0xFFFF.
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