__cpuid, __cpuidex
Microsoft Specific
Generates the cpuid instruction that is available on x86 and x64. This instruction queries the processor for information about the supported features and CPU type.
void __cpuid(
int CPUInfo[4],
int InfoType
);
void __cpuidex(
int CPUInfo[4],
int InfoType,
int ECXValue
);
Parameters
[out] CPUInfo
An array of four integers that contains the gathered information about supported features and the CPU.[in] InfoType
A code that indicates what information this instruction retrieves.[in] ECXValue
The value of the ECX register before this intrinsic generates the cpuid instruction.
Requirements
Intrinsic |
Architecture |
|---|---|
__cpuid |
x86, x64 |
__cpuidex |
x86, x64 |
Header file <intrin.h>
Remarks
This instruction stores the supported features and CPU information in CPUInfo, an array of four 32-bit integers that is filled with the values of the EAX, EBX, ECX, and EDX registers (in that order) after you call the cpuid instruction. The information has a different meaning depending on the value passed as the InfoType parameter. The information returned with various values of InfoType is processor-dependent.
The __cpuidex intrinsic sets the value of the ECX register before it generates the cpuid instruction. This enables you to gather additional information about the processor.
When the InfoType argument is 0, the following table describes the output.
Information Returned
Array index |
Bit range |
Description |
|---|---|---|
0 |
0-31 |
Maximum value for the InfoType parameter that will return valid information. |
1 |
0-31 |
Identification string (part 1) |
2 |
0-31 |
Identification string (part 3) |
3 |
0-31 |
Identification string (part 2) |
When the InfoType argument is 1, the following table describes the output.
CPU Information Returned
Array index |
Bit range |
Description |
|---|---|---|
0 |
0-3 |
Stepping ID |
0 |
4-7 |
Model |
0 |
8-11 |
Family |
0 |
12-13 |
Processor type (Intel) Reserved (AMD) |
0 |
14-15 |
Reserved |
0 |
16-19 |
Extended model |
0 |
20-27 |
Extended family |
0 |
28-31 |
Reserved |
1 |
0-7 |
Brand index |
1 |
8-15 |
The size of the CLFLUSH cache line, in quadwords |
1 |
16-23 |
Logical processor count |
1 |
24-31 |
Initial APIC ID |
2 |
0 |
SSE3 new instructions |
2 |
1-2 |
Reserved |
2 |
3 |
MONITOR/MWAIT |
2 |
4 |
CPL Qualified Debug Store (Intel) Reserved (AMD) |
2 |
5 |
Virtual machine extensions (Intel) Reserved (AMD) |
2 |
6 |
Safer mode extensions (Intel) Reserved (AMD) |
2 |
7 |
Enhanced Intel SpeedStep technology (Intel) Reserved (AMD) |
2 |
8 |
Thermal Monitor (Intel) Reserved (AMD)2 |
2 |
9 |
Supplemental Streaming SIMD Extensions 3 (SSSE3) |
2 |
10 |
L1 context ID (Intel) Reserved (AMD) |
2 |
11 |
Reserved |
2 |
12 |
256-bit FMA extensions (Intel) Reserved (AMD) |
2 |
13 |
CMPXCHG16B support |
2 |
14 |
xTPR update control |
2 |
15 |
Perf/Debug capability MSR |
2 |
16-17 |
Reserved |
2 |
18 |
Direct cache access (DCA) support (Intel) Reserved (AMD) |
2 |
19 |
SSE4.1 extensions |
2 |
20 |
SSE4.2 extensions |
2 |
21 |
x2APIC support (Intel) Reserved (AMD) |
2 |
22 |
MOVBE support (Intel) Reserved (AMD) |
2 |
23 |
POPCNT instruction support |
2 |
24 |
Reserved |
2 |
25 |
AES support (Intel) Reserved (AMD) |
2 |
26 |
XSAVE support (Intel) Reserved (AMD) |
2 |
27 |
OSXSAVE support (Intel) Reserved (AMD) |
2 |
28 |
256-bit Intel advanced vector extensions (Intel) Reserved (AMD) |
2 |
29-31 |
Reserved |
3 |
0-31 |
Feature information (see later in the topic) |
The following table shows the meaning of the feature information value, the value of EDX which is written to CPUInfo[3], when the InfoType argument is 1.
Feature Information Returned
Bit |
Mnemonic |
Description |
|---|---|---|
0 |
FPU |
x87 FPU on chip |
1 |
VME |
Virtual-8086 mode enhancement |
2 |
DE |
Debugging extensions |
3 |
PSE |
Page size extensions |
4 |
TSC |
Time stamp counter |
5 |
MSR |
RDMSR and WRMSR support |
6 |
PAE |
Physical address extensions |
7 |
MCE |
Machine check exception |
8 |
CX8 |
CMPXCHG8B instruction |
9 |
APIC |
APIC on chip |
10 |
n/a |
Reserved |
11 |
SEP |
SYSENTER and SYSEXIT |
12 |
MTRR |
Memory type range registers |
13 |
PGE |
PTE global bit |
14 |
MCA |
Machine check architecture |
15 |
CMOV |
Conditional move/compare instruction |
16 |
PAT |
Page Attribute Table |
17 |
PSE-36 |
36-bit page size extension |
18 |
PSN |
Processor serial number |
19 |
CLFSH |
CFLUSH instruction |
20 |
n/a |
Reserved |
21 |
DS |
Debug store |
22 |
ACPI |
Thermal monitor and clock control |
23 |
MMX |
MMX technology |
24 |
FXSR |
FXSAVE/FXRSTOR |
25 |
SSE |
SSE extensions |
26 |
SSE2 |
SSE2 extensions |
27 |
SS |
Self snoop |
28 |
HTT |
Multithreading |
29 |
TM |
Thermal monitor |
30 |
n/a |
Reserved |
31 |
PBE |
Pending break enable |
Observação
With the AMD chipset, all multi-core AMD CPUs set bit 28 of the feature information bits to indicate that the chip has more than one core. This is the case even though AMD does not support hyper-threading.
Some processors, such as the SSE3 and SSE4-enabled processors, support additional InfoType values. When the InfoType argument is 2, this instruction returns cache information in encoded forms.
The following table shows the values this instruction returns when you set InfoType to 4. This is cache information is related to one of the cache levels. To retrieve this information, you must set the ECX register. Use the __cpuidex intrinsic to set ECX to the zero-based index for the cache level to query.
Deterministic Cache Information
Array Index |
Bit Range |
Description |
|---|---|---|
0 |
0-4 |
Cache type field |
0 |
5-7 |
Cache level |
0 |
8 |
Self-initializing cache |
0 |
9 |
Fully associative cache |
0 |
10-13 |
Reserved |
0 |
14-25 |
Maximum number of threads |
0 |
26-31 |
Maximum number of IDs for processor cores |
1 |
0-11 |
System coherency line size |
1 |
12-21 |
Physical line partitions |
1 |
22-31 |
Ways of associativity |
2 |
0-31 |
Number of sets |
3 |
0-31 |
Reserved |
When InfoType is 5, these processors return information about the monitor feature (see _mm_monitor).
When InfoType is 6, processors return information about the digital temperature and power management.
When InfoType is 0x0A, these processers return information obtained by monitoring the architectural performance.
Some processors support Extended Function CPUID information. If this is supported, InfoType values from 0x80000000 might be used to return information. To determine the maximum meaningful value allowed, set InfoType to 0x80000000. The maximum value of InfoType supported will be written to CPUInfo[0]. The following table shows values returned using the extended function CPUID information.
Extended Function CPUID Information
InfoType |
Array index |
Bit range |
Information |
|---|---|---|---|
0x80000000 |
0 |
0-31 |
Maximum meaningful value of InfoType for extended function CPUID information. |
0x80000000 |
1-3 |
0-31 |
Reserved. |
0x80000001 |
0 |
0-31 |
Extended processor signature and extended feature bits |
0x80000001 |
1 |
0-31 |
Reserved |
0x80000001 |
2 |
0 |
LAHF/SAHF available in 64-bit mode |
0x80000001 |
2 |
1 |
Core multi-processing legacy mode (CmpLegacy) (AMD) Reserved (Intel) |
0x80000001 |
2 |
2 |
Secure virtual machine (SVM) (AMD) Reserved (Intel) |
0x80000001 |
2 |
3 |
Extended APIC Register Space (ExtApicSpace) (AMD) Reserved (Intel) |
0x80000001 |
2 |
4 |
AltMovCr8 (AMD) Reserved (Intel) |
0x80000001 |
2 |
5 |
LZCNT Support (AMD) Reserved (Intel) |
0x80000001 |
2 |
6 |
SSE4A instruction support (EXTRQ, INSERTQ, MOVNTSD, MOVNTSS) (AMD) Reserved (Intel) |
0x80000001 |
2 |
7 |
Misaligned SSE support mode available (AMD) Reserved (Intel) |
0x80000001 |
2 |
8 |
PREFETCH and PREFETCHW support (AMD) Reserved (Intel) |
0x80000001 |
2 |
9-11 |
Reserved |
0x80000001 |
2 |
12 |
SKINIT and DEV support (AMD) Reserved (Intel) |
0x80000001 |
2 |
13-31 |
Reserved |
0x80000001 |
3 |
0-10 |
Reserved |
0x80000001 |
3 |
11 |
SYSCALL/SYSRET available in 64-bit mode |
0x80000001 |
3 |
12-19 |
Reserved |
0x80000001 |
3 |
20 |
Execute disable bit available |
0x80000001 |
3 |
21 |
Reserved |
0x80000001 |
3 |
22 |
Extensions to MMX instructions (AMD) Reserved (Intel) |
0x80000001 |
3 |
23-24 |
Reserved |
0x80000001 |
3 |
25 |
FFXSR (AMD) Reserved (Intel) |
0x80000001 |
3 |
26 |
1GB page support (AMD) Reserved (Intel) |
0x80000001 |
3 |
27 |
RDTSCP support (AMD) Reserved (Intel) |
0x80000001 |
3 |
28 |
Reserved |
0x80000001 |
3 |
29 |
64-bit technology available |
0x80000001 |
3 |
30 |
3DnowExt (AMD) Reserved (Intel) |
0x80000001 |
3 |
31 |
3Dnow! instructions (AMD) Reserved (Intel) |
0x80000002 |
0-3 |
0-31 |
Processor brand string |
0x80000003 |
0-3 |
0-31 |
Processor brand string, continued |
0x80000004 |
0-3 |
0-31 |
Processor brand string, continued |
0x80000005 |
0-3 |
0-31 |
L1 cache and TLB identifiers (AMD) Reserved (Intel) |
0x80000006 |
0-1 |
0-31 |
Reserved |
0x80000006 |
2 |
0-7 |
Cache line size |
0x80000006 |
2 |
8-11 |
Reserved |
0x80000006 |
2 |
12-15 |
L2 associativity |
0x80000006 |
2 |
16-31 |
Cache size in 1K units |
0x80000006 |
3 |
0-31 |
Reserved |
0x80000007 |
0-3 |
0-31 |
Advanced power management information (AMD) Reserved (Intel) |
0x80000008 |
0 |
0-7 |
Physical address bits |
0x80000008 |
0 |
8-15 |
Virtual address bits |
0x80000008 |
0 |
16-31 |
Reserved |
0x80000008 |
1-3 |
0-31 |
Reserved |
0x8000000A |
0 |
0-7 |
SVM revision (AMD) Reserved (Intel) |
0x8000000A |
0 |
8-31 |
Reserved |
0x8000000A |
1 |
0-31 |
NASID - Number of Address Space Identifiers (AMD) Reserved (Intel) |
0x8000000A |
2 |
0-31 |
Reserved |
0x8000000A |
3 |
0 |
Nested paging (AMD) Reserved (Intel) |
0x8000000A |
3 |
1 |
LBR visualization (AMD) Reserved (Intel) |
0x8000000A |
3 |
2-31 |
Reserved |
0x80000019 |
0-3 |
0-31 |
TLB 1GB page identifiers (AMD) Reserved (Intel) |
0x8000001A |
0 |
0 |
FP128 optimization (AMD) Reserved (Intel) |
0x8000001A |
0 |
1 |
MOVU, MOVUPS, MOVUPD optimization over MOVL/MOVH, MOVHLPS/MOVHPS, MOVLPD/MOVHPD (AMD) Reserved (Intel) |
0x8000001A |
0 |
2-31 |
Reserved |
0x8000001A |
1-3 |
0-31 |
Reserved |
Example
// cpuid.cpp
// processor: x86, x64
// Use the __cpuid intrinsic to get information about a CPU
#include <stdio.h>
#include <string.h>
#include <intrin.h>
const char* szFeatures[] =
{
"x87 FPU On Chip",
"Virtual-8086 Mode Enhancement",
"Debugging Extensions",
"Page Size Extensions",
"Time Stamp Counter",
"RDMSR and WRMSR Support",
"Physical Address Extensions",
"Machine Check Exception",
"CMPXCHG8B Instruction",
"APIC On Chip",
"Unknown1",
"SYSENTER and SYSEXIT",
"Memory Type Range Registers",
"PTE Global Bit",
"Machine Check Architecture",
"Conditional Move/Compare Instruction",
"Page Attribute Table",
"36-bit Page Size Extension",
"Processor Serial Number",
"CFLUSH Extension",
"Unknown2",
"Debug Store",
"Thermal Monitor and Clock Ctrl",
"MMX Technology",
"FXSAVE/FXRSTOR",
"SSE Extensions",
"SSE2 Extensions",
"Self Snoop",
"Multithreading Technology",
"Thermal Monitor",
"Unknown4",
"Pending Break Enable"
};
int main(int argc, char* argv[])
{
char CPUString[0x20];
char CPUBrandString[0x40];
int CPUInfo[4] = {-1};
int nSteppingID = 0;
int nModel = 0;
int nFamily = 0;
int nProcessorType = 0;
int nExtendedmodel = 0;
int nExtendedfamily = 0;
int nBrandIndex = 0;
int nCLFLUSHcachelinesize = 0;
int nLogicalProcessors = 0;
int nAPICPhysicalID = 0;
int nFeatureInfo = 0;
int nCacheLineSize = 0;
int nL2Associativity = 0;
int nCacheSizeK = 0;
int nPhysicalAddress = 0;
int nVirtualAddress = 0;
int nRet = 0;
int nCores = 0;
int nCacheType = 0;
int nCacheLevel = 0;
int nMaxThread = 0;
int nSysLineSize = 0;
int nPhysicalLinePartitions = 0;
int nWaysAssociativity = 0;
int nNumberSets = 0;
unsigned nIds, nExIds, i;
bool bSSE3Instructions = false;
bool bMONITOR_MWAIT = false;
bool bCPLQualifiedDebugStore = false;
bool bVirtualMachineExtensions = false;
bool bEnhancedIntelSpeedStepTechnology = false;
bool bThermalMonitor2 = false;
bool bSupplementalSSE3 = false;
bool bL1ContextID = false;
bool bCMPXCHG16B = false;
bool bxTPRUpdateControl = false;
bool bPerfDebugCapabilityMSR = false;
bool bSSE41Extensions = false;
bool bSSE42Extensions = false;
bool bPOPCNT = false;
bool bMultithreading = false;
bool bLAHF_SAHFAvailable = false;
bool bCmpLegacy = false;
bool bSVM = false;
bool bExtApicSpace = false;
bool bAltMovCr8 = false;
bool bLZCNT = false;
bool bSSE4A = false;
bool bMisalignedSSE = false;
bool bPREFETCH = false;
bool bSKINITandDEV = false;
bool bSYSCALL_SYSRETAvailable = false;
bool bExecuteDisableBitAvailable = false;
bool bMMXExtensions = false;
bool bFFXSR = false;
bool b1GBSupport = false;
bool bRDTSCP = false;
bool b64Available = false;
bool b3DNowExt = false;
bool b3DNow = false;
bool bNestedPaging = false;
bool bLBRVisualization = false;
bool bFP128 = false;
bool bMOVOptimization = false;
bool bSelfInit = false;
bool bFullyAssociative = false;
// __cpuid with an InfoType argument of 0 returns the number of
// valid Ids in CPUInfo[0] and the CPU identification string in
// the other three array elements. The CPU identification string is
// not in linear order. The code below arranges the information
// in a human readable form.
__cpuid(CPUInfo, 0);
nIds = CPUInfo[0];
memset(CPUString, 0, sizeof(CPUString));
*((int*)CPUString) = CPUInfo[1];
*((int*)(CPUString+4)) = CPUInfo[3];
*((int*)(CPUString+8)) = CPUInfo[2];
// Get the information associated with each valid Id
for (i=0; i<=nIds; ++i)
{
__cpuid(CPUInfo, i);
printf_s("\nFor InfoType %d\n", i);
printf_s("CPUInfo[0] = 0x%x\n", CPUInfo[0]);
printf_s("CPUInfo[1] = 0x%x\n", CPUInfo[1]);
printf_s("CPUInfo[2] = 0x%x\n", CPUInfo[2]);
printf_s("CPUInfo[3] = 0x%x\n", CPUInfo[3]);
// Interpret CPU feature information.
if (i == 1)
{
nSteppingID = CPUInfo[0] & 0xf;
nModel = (CPUInfo[0] >> 4) & 0xf;
nFamily = (CPUInfo[0] >> 8) & 0xf;
nProcessorType = (CPUInfo[0] >> 12) & 0x3;
nExtendedmodel = (CPUInfo[0] >> 16) & 0xf;
nExtendedfamily = (CPUInfo[0] >> 20) & 0xff;
nBrandIndex = CPUInfo[1] & 0xff;
nCLFLUSHcachelinesize = ((CPUInfo[1] >> 8) & 0xff) * 8;
nLogicalProcessors = ((CPUInfo[1] >> 16) & 0xff);
nAPICPhysicalID = (CPUInfo[1] >> 24) & 0xff;
bSSE3Instructions = (CPUInfo[2] & 0x1) || false;
bMONITOR_MWAIT = (CPUInfo[2] & 0x8) || false;
bCPLQualifiedDebugStore = (CPUInfo[2] & 0x10) || false;
bVirtualMachineExtensions = (CPUInfo[2] & 0x20) || false;
bEnhancedIntelSpeedStepTechnology = (CPUInfo[2] & 0x80) || false;
bThermalMonitor2 = (CPUInfo[2] & 0x100) || false;
bSupplementalSSE3 = (CPUInfo[2] & 0x200) || false;
bL1ContextID = (CPUInfo[2] & 0x300) || false;
bCMPXCHG16B= (CPUInfo[2] & 0x2000) || false;
bxTPRUpdateControl = (CPUInfo[2] & 0x4000) || false;
bPerfDebugCapabilityMSR = (CPUInfo[2] & 0x8000) || false;
bSSE41Extensions = (CPUInfo[2] & 0x80000) || false;
bSSE42Extensions = (CPUInfo[2] & 0x100000) || false;
bPOPCNT= (CPUInfo[2] & 0x800000) || false;
nFeatureInfo = CPUInfo[3];
bMultithreading = (nFeatureInfo & (1 << 28)) || false;
}
}
// Calling __cpuid with 0x80000000 as the InfoType argument
// gets the number of valid extended IDs.
__cpuid(CPUInfo, 0x80000000);
nExIds = CPUInfo[0];
memset(CPUBrandString, 0, sizeof(CPUBrandString));
// Get the information associated with each extended ID.
for (i=0x80000000; i<=nExIds; ++i)
{
__cpuid(CPUInfo, i);
printf_s("\nFor InfoType %x\n", i);
printf_s("CPUInfo[0] = 0x%x\n", CPUInfo[0]);
printf_s("CPUInfo[1] = 0x%x\n", CPUInfo[1]);
printf_s("CPUInfo[2] = 0x%x\n", CPUInfo[2]);
printf_s("CPUInfo[3] = 0x%x\n", CPUInfo[3]);
if (i == 0x80000001)
{
bLAHF_SAHFAvailable = (CPUInfo[2] & 0x1) || false;
bCmpLegacy = (CPUInfo[2] & 0x2) || false;
bSVM = (CPUInfo[2] & 0x4) || false;
bExtApicSpace = (CPUInfo[2] & 0x8) || false;
bAltMovCr8 = (CPUInfo[2] & 0x10) || false;
bLZCNT = (CPUInfo[2] & 0x20) || false;
bSSE4A = (CPUInfo[2] & 0x40) || false;
bMisalignedSSE = (CPUInfo[2] & 0x80) || false;
bPREFETCH = (CPUInfo[2] & 0x100) || false;
bSKINITandDEV = (CPUInfo[2] & 0x1000) || false;
bSYSCALL_SYSRETAvailable = (CPUInfo[3] & 0x800) || false;
bExecuteDisableBitAvailable = (CPUInfo[3] & 0x10000) || false;
bMMXExtensions = (CPUInfo[3] & 0x40000) || false;
bFFXSR = (CPUInfo[3] & 0x200000) || false;
b1GBSupport = (CPUInfo[3] & 0x400000) || false;
bRDTSCP = (CPUInfo[3] & 0x8000000) || false;
b64Available = (CPUInfo[3] & 0x20000000) || false;
b3DNowExt = (CPUInfo[3] & 0x40000000) || false;
b3DNow = (CPUInfo[3] & 0x80000000) || false;
}
// Interpret CPU brand string and cache information.
if (i == 0x80000002)
memcpy(CPUBrandString, CPUInfo, sizeof(CPUInfo));
else if (i == 0x80000003)
memcpy(CPUBrandString + 16, CPUInfo, sizeof(CPUInfo));
else if (i == 0x80000004)
memcpy(CPUBrandString + 32, CPUInfo, sizeof(CPUInfo));
else if (i == 0x80000006)
{
nCacheLineSize = CPUInfo[2] & 0xff;
nL2Associativity = (CPUInfo[2] >> 12) & 0xf;
nCacheSizeK = (CPUInfo[2] >> 16) & 0xffff;
}
else if (i == 0x80000008)
{
nPhysicalAddress = CPUInfo[0] & 0xff;
nVirtualAddress = (CPUInfo[0] >> 8) & 0xff;
}
else if (i == 0x8000000A)
{
bNestedPaging = (CPUInfo[3] & 0x1) || false;
bLBRVisualization = (CPUInfo[3] & 0x2) || false;
}
else if (i == 0x8000001A)
{
bFP128 = (CPUInfo[0] & 0x1) || false;
bMOVOptimization = (CPUInfo[0] & 0x2) || false;
}
}
// Display all the information in user-friendly format.
printf_s("\n\nCPU String: %s\n", CPUString);
if (nIds >= 1)
{
if (nSteppingID)
printf_s("Stepping ID = %d\n", nSteppingID);
if (nModel)
printf_s("Model = %d\n", nModel);
if (nFamily)
printf_s("Family = %d\n", nFamily);
if (nProcessorType)
printf_s("Processor Type = %d\n", nProcessorType);
if (nExtendedmodel)
printf_s("Extended model = %d\n", nExtendedmodel);
if (nExtendedfamily)
printf_s("Extended family = %d\n", nExtendedfamily);
if (nBrandIndex)
printf_s("Brand Index = %d\n", nBrandIndex);
if (nCLFLUSHcachelinesize)
printf_s("CLFLUSH cache line size = %d\n",
nCLFLUSHcachelinesize);
if (bMultithreading && (nLogicalProcessors > 0))
printf_s("Logical Processor Count = %d\n", nLogicalProcessors);
if (nAPICPhysicalID)
printf_s("APIC Physical ID = %d\n", nAPICPhysicalID);
if (nFeatureInfo || bSSE3Instructions ||
bMONITOR_MWAIT || bCPLQualifiedDebugStore ||
bVirtualMachineExtensions || bEnhancedIntelSpeedStepTechnology ||
bThermalMonitor2 || bSupplementalSSE3 || bL1ContextID ||
bCMPXCHG16B || bxTPRUpdateControl || bPerfDebugCapabilityMSR ||
bSSE41Extensions || bSSE42Extensions || bPOPCNT ||
bLAHF_SAHFAvailable || bCmpLegacy || bSVM ||
bExtApicSpace || bAltMovCr8 ||
bLZCNT || bSSE4A || bMisalignedSSE ||
bPREFETCH || bSKINITandDEV || bSYSCALL_SYSRETAvailable ||
bExecuteDisableBitAvailable || bMMXExtensions || bFFXSR || b1GBSupport ||
bRDTSCP || b64Available || b3DNowExt || b3DNow || bNestedPaging ||
bLBRVisualization || bFP128 || bMOVOptimization )
{
printf_s("\nThe following features are supported:\n");
if (bSSE3Instructions)
printf_s("\tSSE3\n");
if (bMONITOR_MWAIT)
printf_s("\tMONITOR/MWAIT\n");
if (bCPLQualifiedDebugStore)
printf_s("\tCPL Qualified Debug Store\n");
if (bVirtualMachineExtensions)
printf_s("\tVirtual Machine Extensions\n");
if (bEnhancedIntelSpeedStepTechnology)
printf_s("\tEnhanced Intel SpeedStep Technology\n");
if (bThermalMonitor2)
printf_s("\tThermal Monitor 2\n");
if (bSupplementalSSE3)
printf_s("\tSupplemental Streaming SIMD Extensions 3\n");
if (bL1ContextID)
printf_s("\tL1 Context ID\n");
if (bCMPXCHG16B)
printf_s("\tCMPXCHG16B Instruction\n");
if (bxTPRUpdateControl)
printf_s("\txTPR Update Control\n");
if (bPerfDebugCapabilityMSR)
printf_s("\tPerf\\Debug Capability MSR\n");
if (bSSE41Extensions)
printf_s("\tSSE4.1 Extensions\n");
if (bSSE42Extensions)
printf_s("\tSSE4.2 Extensions\n");
if (bPOPCNT)
printf_s("\tPPOPCNT Instruction\n");
i = 0;
nIds = 1;
while (i < (sizeof(szFeatures)/sizeof(const char*)))
{
if (nFeatureInfo & nIds)
{
printf_s("\t");
printf_s(szFeatures[i]);
printf_s("\n");
}
nIds <<= 1;
++i;
}
if (bLAHF_SAHFAvailable)
printf_s("\tLAHF/SAHF in 64-bit mode\n");
if (bCmpLegacy)
printf_s("\tCore multi-processing legacy mode\n");
if (bSVM)
printf_s("\tSecure Virtual Machine\n");
if (bExtApicSpace)
printf_s("\tExtended APIC Register Space\n");
if (bAltMovCr8)
printf_s("\tAltMovCr8\n");
if (bLZCNT)
printf_s("\tLZCNT instruction\n");
if (bSSE4A)
printf_s("\tSSE4A (EXTRQ, INSERTQ, MOVNTSD, MOVNTSS)\n");
if (bMisalignedSSE)
printf_s("\tMisaligned SSE mode\n");
if (bPREFETCH)
printf_s("\tPREFETCH and PREFETCHW Instructions\n");
if (bSKINITandDEV)
printf_s("\tSKINIT and DEV support\n");
if (bSYSCALL_SYSRETAvailable)
printf_s("\tSYSCALL/SYSRET in 64-bit mode\n");
if (bExecuteDisableBitAvailable)
printf_s("\tExecute Disable Bit\n");
if (bMMXExtensions)
printf_s("\tExtensions to MMX Instructions\n");
if (bFFXSR)
printf_s("\tFFXSR\n");
if (b1GBSupport)
printf_s("\t1GB page support\n");
if (bRDTSCP)
printf_s("\tRDTSCP instruction\n");
if (b64Available)
printf_s("\t64 bit Technology\n");
if (b3DNowExt)
printf_s("\t3Dnow Ext\n");
if (b3DNow)
printf_s("\t3Dnow! instructions\n");
if (bNestedPaging)
printf_s("\tNested Paging\n");
if (bLBRVisualization)
printf_s("\tLBR Visualization\n");
if (bFP128)
printf_s("\tFP128 optimization\n");
if (bMOVOptimization)
printf_s("\tMOVU Optimization\n");
}
}
if (nExIds >= 0x80000004)
printf_s("\nCPU Brand String: %s\n", CPUBrandString);
if (nExIds >= 0x80000006)
{
printf_s("Cache Line Size = %d\n", nCacheLineSize);
printf_s("L2 Associativity = %d\n", nL2Associativity);
printf_s("Cache Size = %dK\n", nCacheSizeK);
}
for (i=0;;i++)
{
__cpuidex(CPUInfo, 0x4, i);
if(!(CPUInfo[0] & 0xf0)) break;
if(i == 0)
{
nCores = CPUInfo[0] >> 26;
printf_s("\n\nNumber of Cores = %d\n", nCores + 1);
}
nCacheType = (CPUInfo[0] & 0x1f);
nCacheLevel = (CPUInfo[0] & 0xe0) >> 5;
bSelfInit = (CPUInfo[0] & 0x100) >> 8;
bFullyAssociative = (CPUInfo[0] & 0x200) >> 9;
nMaxThread = (CPUInfo[0] & 0x03ffc000) >> 14;
nSysLineSize = (CPUInfo[1] & 0x0fff);
nPhysicalLinePartitions = (CPUInfo[1] & 0x03ff000) >> 12;
nWaysAssociativity = (CPUInfo[1]) >> 22;
nNumberSets = CPUInfo[2];
printf_s("\n");
printf_s("ECX Index %d\n", i);
switch (nCacheType)
{
case 0:
printf_s(" Type: Null\n");
break;
case 1:
printf_s(" Type: Data Cache\n");
break;
case 2:
printf_s(" Type: Instruction Cache\n");
break;
case 3:
printf_s(" Type: Unified Cache\n");
break;
default:
printf_s(" Type: Unknown\n");
}
printf_s(" Level = %d\n", nCacheLevel + 1);
if (bSelfInit)
{
printf_s(" Self Initializing\n");
}
else
{
printf_s(" Not Self Initializing\n");
}
if (bFullyAssociative)
{
printf_s(" Is Fully Associatve\n");
}
else
{
printf_s(" Is Not Fully Associatve\n");
}
printf_s(" Max Threads = %d\n",
nMaxThread+1);
printf_s(" System Line Size = %d\n",
nSysLineSize+1);
printf_s(" Physical Line Partions = %d\n",
nPhysicalLinePartitions+1);
printf_s(" Ways of Associativity = %d\n",
nWaysAssociativity+1);
printf_s(" Number of Sets = %d\n",
nNumberSets+1);
}
return nRet;
}
For InfoType 0
CPUInfo[0] = 0x5
CPUInfo[1] = 0x756e6547
CPUInfo[2] = 0x6c65746e
CPUInfo[3] = 0x49656e69
For InfoType 1
CPUInfo[0] = 0xf4a
CPUInfo[1] = 0x1020800
CPUInfo[2] = 0x659d
CPUInfo[3] = 0xbfebfbff
For InfoType 2
CPUInfo[0] = 0x605b5001
CPUInfo[1] = 0x0
CPUInfo[2] = 0x0
CPUInfo[3] = 0x7d7040
For InfoType 3
CPUInfo[0] = 0x0
CPUInfo[1] = 0x0
CPUInfo[2] = 0x0
CPUInfo[3] = 0x0
For InfoType 4
CPUInfo[0] = 0x0
CPUInfo[1] = 0x0
CPUInfo[2] = 0x0
CPUInfo[3] = 0x0
For InfoType 5
CPUInfo[0] = 0x40
CPUInfo[1] = 0x40
CPUInfo[2] = 0x0
CPUInfo[3] = 0x0
For InfoType 80000000
CPUInfo[0] = 0x80000008
CPUInfo[1] = 0x0
CPUInfo[2] = 0x0
CPUInfo[3] = 0x0
For InfoType 80000001
CPUInfo[0] = 0x0
CPUInfo[1] = 0x0
CPUInfo[2] = 0x1
CPUInfo[3] = 0x20100000
For InfoType 80000002
CPUInfo[0] = 0x20202020
CPUInfo[1] = 0x20202020
CPUInfo[2] = 0x20202020
CPUInfo[3] = 0x6e492020
For InfoType 80000003
CPUInfo[0] = 0x286c6574
CPUInfo[1] = 0x50202952
CPUInfo[2] = 0x69746e65
CPUInfo[3] = 0x52286d75
For InfoType 80000004
CPUInfo[0] = 0x20342029
CPUInfo[1] = 0x20555043
CPUInfo[2] = 0x30362e33
CPUInfo[3] = 0x7a4847
For InfoType 80000005
CPUInfo[0] = 0x0
CPUInfo[1] = 0x0
CPUInfo[2] = 0x0
CPUInfo[3] = 0x0
For InfoType 80000006
CPUInfo[0] = 0x0
CPUInfo[1] = 0x0
CPUInfo[2] = 0x8006040
CPUInfo[3] = 0x0
For InfoType 80000007
CPUInfo[0] = 0x0
CPUInfo[1] = 0x0
CPUInfo[2] = 0x0
CPUInfo[3] = 0x0
For InfoType 80000008
CPUInfo[0] = 0x3024
CPUInfo[1] = 0x0
CPUInfo[2] = 0x0
CPUInfo[3] = 0x0
CPU String: GenuineIntel
Stepping ID = 10
Model = 4
Family = 15
CLFLUSH cache line size = 64
Logical Processor Count = 2
APIC Physical ID = 1
The following features are supported:
SSE3
MONITOR/MWAIT
CPL Qualified Debug Store
Enhanced Intel SpeedStep Technology
Thermal Monitor 2
L1 Context ID
CMPXCHG16B Instruction
xTPR Update Control
x87 FPU On Chip
Virtual-8086 Mode Enhancement
Debugging Extensions
Page Size Extensions
Time Stamp Counter
RDMSR and WRMSR Support
Physical Address Extensions
Machine Check Exception
CMPXCHG8B Instruction
APIC On Chip
SYSENTER and SYSEXIT
Memory Type Range Registers
PTE Global Bit
Machine Check Architecture
Conditional Move/Compare Instruction
Page Attribute Table
36-bit Page Size Extension
CFLUSH Extension
Debug Store
Thermal Monitor and Clock Ctrl
MMX Technology
FXSAVE/FXRSTOR
SSE Extensions
SSE2 Extensions
Self Snoop
Multithreading Technology
Thermal Monitor
Pending Break Enable
LAHF/SAHF in 64-bit mode
64 bit Technology
CPU Brand String: Intel(R) Pentium(R) 4 CPU 3.60GHz
Cache Line Size = 64
L2 Associativity = 6
Cache Size = 2048K
Number of Cores = 1
ECX Index 0
Type: Data Cache
Level = 2
Self Initializing
Is Not Fully Associatve
Max Threads = 2
System Line Size = 64
Physical Line Partions = 1
Ways of Associativity = 8
Number of Sets = 32
ECX Index 1
Type: Unified Cache
Level = 3
Self Initializing
Is Not Fully Associatve
Max Threads = 2
System Line Size = 64
Physical Line Partions = 2
Ways of Associativity = 8
Number of Sets = 2048